Build the virtual platforms that turn imec's CPU architectures into runnable systems — before silicon.
Compute System Architecture (CSA) is imec's center of excellence for hardware-software-technology co-design of future compute systems. We work in close collaboration with imec's expertise centers in applications, technology, circuits, and design to innovate and pathfind next-generation compute architectures across AI, HPC, automotive, space, and other domains. CSA operates across six imec centers — Belgium, the Netherlands, Germany, the UK, the USA, and Qatar. This position is based primarily in Leuven, Belgium.
We are looking for a SystemC / TLM-2.0 Modeling Engineer to join the Platform, Prototypes and Physical-Aware Design (P3D) group, focusing on the CPU subsystem of imec's RISC-V-based compute platforms. You will develop SystemC TLM-2.0 models of CPU cores, caches, memory hierarchy, and the surrounding interconnect — enabling architectural exploration, early software enablement, and pre-silicon performance analysis.
Your models are the bridge between architecture and implementation: they let our architects evaluate design choices before committing to RTL, they let software teams start porting and tuning long before silicon is back, and they feed directly into the validation infrastructure that surrounds imec's prototype demonstrators — the silicon vehicles for imec's CMOS 2.0 vision of functionally partitioned, 3D-integrated compute systems beyond what monolithic SoCs can deliver.
What you will do
- Develop SystemC TLM-2.0 models of the CPU subsystem — cores, caches, memory controllers, on-chip interconnect — at both loosely-timed (LT) and approximately-timed (AT) abstraction levels.
- Assemble and maintain virtual platforms that integrate these models with peripheral and system IP, enabling full-system simulation and early software bring-up.
- Drive architectural exploration studies in close collaboration with SoC and chiplet architects: micro-architectural what-ifs, partitioning trade-offs, memory hierarchy sweeps, and chiplet interconnect dimensioning for CMOS 2.0 systems.
- Define and run pre-silicon performance analysis flows — workload characterization, bottleneck identification, and PPA-relevant trade-off studies.
- Support hybrid RTL/TLM co-simulation environments to validate model fidelity against RTL implementations and to accelerate RTL verification with TLM-driven stimulus.
- Collaborate with the RTL design and verification teams to align model behaviour with implementation and to feed insights back into the architecture loop.
- Document model intent, assumptions, and known limitations clearly enough that architects, designers, and software engineers can rely on the model with confidence.
- This is a temporary contract of two years, with the possibility to extend the contract.
What we do for you
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.
We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.
Who you are
- At least 5 years of hands-on experience developing SystemC models with TLM-2.0 for CPU, SoC, or memory subsystems.
- Strong modern C++ (C++11 and beyond), with the discipline to write models that are fast, maintainable, and trustworthy.
- Solid understanding of CPU and SoC architecture — pipelines, caches, coherency, memory ordering, interconnect protocols — at a level that lets you turn an architectural spec into a faithful executable model.
- Practical familiarity with both LT and AT modeling styles and the trade-offs between simulation speed and timing fidelity.
- Experience building or extending virtual platforms (e.g. Synopsys Virtualizer, Arm Fast Models, Imperas, gem5, QEMU, or in-house frameworks).
- Comfort with scripting (Python, Tcl) for model build flows, regressions, and analysis automation.
- Excellent written and spoken English, with the documentation habits to match.
- A structured, transparent way of working and a collaborative attitude in a multidisciplinary, multicultural team.
Considered an asset:
- Experience modeling RISC-V cores or RISC-V-based subsystems.
- Exposure to hybrid TLM/RTL co-simulation and to driving RTL verification with TLM stimulus.
- Familiarity with High-Level Synthesis (HLS) flows that consume algorithmic SystemC and produce synthesizable RTL.
- Experience with performance modeling of multi-die / chiplet systems and die-to-die interconnects (UCIe or similar).
- Awareness of physical-aware design considerations and how they propagate back into architectural modeling.
